r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 446

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 10.10 TPSC1 and TPSC0 (Channel 5)
Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value
10.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Rev. 2.00 Dec. 09, 2005 Page 422 of 1152
REJ09B0191-0200
Channel
5
Bit
7
6
should always be 0.
Bit Name
—
BFE
Timer Mode Register (TMDR)
Bit 1
TPSC1
1
0
Initial value:
Initial
Value
0
0
Bit 0
TPSC0
0
1
0
1
R/W:
Bit:
R
7
0
-
R/W
R
R/W
Description
Internal clock: counts on Pφ/1
Internal clock: counts on Pφ/4
Internal clock: counts on Pφ/16
Internal clock: counts on Pφ/64
R/W
BFE
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
R/W
BFB
5
0
operation
R/W
BFA
4
0
R/W
3
0
R/W
2
0
MD[3:0]
R/W
1
0
R/W
0
0