r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 34

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 1 Overview
Rev. 2.00 Dec. 09, 2005 Page 10 of 1152
REJ09B0191-0200
Classification
Operating mode
control
System control
Symbol
MD2, MD0
MD_CLK2,
MD_CLK0
ASEMD
RES
MRES
WDTOVF
BREQ
BACK
I/O
I
I
I
I
I
O
I
O
Name
Mode set
Clock mode set
Debugging mode Enables the E10A-USB emulator
Power-on reset
Manual reset
Watchdog timer
overflow
Bus-mastership
request
Bus-mastership
request
acknowledge
Function
Sets the operating mode. Do not
change the signal levels on these
pins during operation.
Sets the clock operating mode. Do
not change the signal levels on these
pins during operation.
functions.
Input a high level to operate the LSI
in normal mode (not in debugging
mode). To operate it in debugging
mode, apply a low level to this pin on
the user system board.
This LSI enters the power-on reset
state when this signal goes low.
This LSI enters the manual reset
state when this signal goes low.
Outputs an overflow signal from the
WDT.
A low level is input to this pin when
an external device requests the
release of the bus mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.