r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 204

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Cache
(1)
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid.
The U bit (only for operand cache) indicates whether the entry has been written to in write-back
mode. When the U bit is 1, the entry has been written to; when 0, it has not.
The tag address holds the physical address used in the external memory access. It consists of 21
bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses
of the cache-enabled space are H'00000000 to H'1FFFFFFF (see section 8, Bus State Controller
(BSC)), and therefore the upper three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in
software standby mode. The tag address is not initialized by a power-on reset or manual reset or in
software standby mode.
(2)
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes).
The data array is not initialized by a power-on reset or manual reset or in software standby mode.
Rev. 2.00 Dec. 09, 2005 Page 180 of 1152
REJ09B0191-0200
Address Array
Data Array
Entry 127
Entry 0
Entry 1
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V U
23 (1 + 1 + 21) bits
Address array (ways 0 to 3)
Tag address
Figure 7.1 Operand Cache Structure
127
0
1
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LW0
LW0 to LW3: Longword data 0 to 3
LW1
128 (32 × 4) bits
Data array (ways 0 to 3)
LW2
LW3
127
0
1
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LRU
6 bits