r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 11

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

4.7
4.8
4.9
Section 5 Interrupt Controller (INTC) ...............................................................111
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
When Exception Sources Are Not Accepted ..................................................................... 106
Stack Status after Exception Handling Ends...................................................................... 107
Usage Notes ....................................................................................................................... 109
4.9.1
4.9.2
4.9.3
Features.............................................................................................................................. 111
Input/Output Pins ............................................................................................................... 113
Register Descriptions ......................................................................................................... 114
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Interrupt Sources................................................................................................................ 127
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
Interrupt Exception Handling Vector Table and Priority................................................... 130
Operation ........................................................................................................................... 139
5.6.1
5.6.2
Interrupt Response Time.................................................................................................... 143
Register Banks ................................................................................................................... 149
5.8.1
5.8.2
5.8.3
5.8.4
5.8.5
Data Transfer with Interrupt Request Signals .................................................................... 154
Value of Stack Pointer (SP) .................................................................................. 109
Value of Vector Base Register (VBR) .................................................................. 109
Address Errors Caused by Stacking of Address Error Exception Handling ......... 109
Interrupt Priority Registers 01, 02, 05 to 14 (IPR01, IPR02, IPR05 to IPR14) .... 115
Interrupt Control Register 0 (ICR0)...................................................................... 117
Interrupt Control Register 1 (ICR1)...................................................................... 118
Interrupt Control Register 2 (ICR2)...................................................................... 119
IRQ Interrupt Request Register (IRQRR)............................................................. 120
PINT Interrupt Enable Register (PINTER)........................................................... 122
PINT Interrupt Request Register (PIRR) .............................................................. 123
Bank Control Register (IBCR).............................................................................. 124
Bank Number Register (IBNR) ............................................................................ 125
NMI Interrupt........................................................................................................ 127
User Break Interrupt ............................................................................................. 127
H-UDI Interrupt .................................................................................................... 127
IRQ Interrupts ....................................................................................................... 128
PINT Interrupts ..................................................................................................... 128
On-Chip Peripheral Module Interrupts ................................................................. 129
Interrupt Operation Sequence ............................................................................... 139
Stack after Interrupt Exception Handling ............................................................. 142
Banked Register and Input/Output of Banks ........................................................ 150
Bank Save and Restore Operations....................................................................... 150
Save and Restore Operations after Saving to All Banks....................................... 152
Register Bank Exception....................................................................................... 153
Register Bank Error Exception Handling ............................................................. 153
Rev. 2.00 Dec. 09, 2005 Page xi of xxiv