r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 207

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
31 to 12
11
10, 9
8
7 to 4
3
2
1
0
Bit Name

ICF

ICE

OCF

WT
OCE
Initial
Value
All 0
0
All 0
0
All 0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Instruction Cache Flush
Writing 1 flushes all instruction cache entries (clears the
V and LRU bits of all instruction cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the instruction cache is flushed.
Reserved
These bits are always read as 0. The write value should
always be 0.
Instruction Cache Enable
Indicates whether the instruction cache function is
enabled/disabled.
0: Instruction cache disable
1: Instruction cache enable
Reserved
These bits are always read as 0. The write value should
always be 0.
Operand Cache Flush
Writing 1 flushes all operand cache entries (clears the
V, U, and LRU bits of all operand cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the operand cache is flushed.
Reserved
This bit is always read as 0. The write value should
always be 0.
Write Through
Selects write-back mode or write-through mode.
0: Write-back mode
1: Write-through mode
Operand Cache Enable
Indicates whether the operand cache function is
enabled/disabled.
0: Operand cache disable
1: Operand cache enable
Rev. 2.00 Dec. 09, 2005 Page 183 of 1152
REJ09B0191-0200
Section 7 Cache