r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 515

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Table 10.42 Setting of Bits BTE1 and BTE0
Note:
Bit 1
BTE1
0
0
1
1
1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the
to section 10.4.8, Complementary PWM Mode.
timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer
transfer will not be performed.
Bit 0
BTE0
0
1
0
1
Description
Enables transfer from the buffer registers to the temporary registers*
and does not link the transfer with interrupt skipping operation.
Disables transfer from the buffer registers to the temporary registers.
Links transfer from the buffer registers to the temporary registers with
interrupt skipping operation.*
Setting prohibited
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
2
Rev. 2.00 Dec. 09, 2005 Page 491 of 1152
REJ09B0191-0200
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