r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 806

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
15.6.3
1. When the DMAC writes data to SCFTDR due to a TXI interrupt request, the state of the
2. When a channel is being used in full-duplex transmission, in which the DMAC is on the
3. When a channel is being used in full-duplex transmission, in which the DMAC is on the
15.6.4
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set.
Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF
receiver continues to operate.
15.6.5
The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the
serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work.
During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and
SPB2DT bits should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD
pin.
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REJ09B0191-0200
TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer
end flag in such a case.
transmit side and the CPU on the receive side, the RDF or DR flag in the serial status register
(SCFSR) could be cleared after these flags are set and receive data is read from the receive
FIFO data register (SCFRDR).
receive side and the CPU on the transmit side, the TDFE or TEND flag in the serial status
register (SCFSR) could be cleared after these flags are set and transmit data is written to the
transmit FIFO data register (SCFTDR).
Restriction on DMAC Usage
Break Detection and Processing
Sending a Break Signal