r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 775

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
7, 6
5, 4
Bit Name
RTRG[1:0]
TTRG[1:0]
Initial
Value
00
00
R/W
R/W
R/W
Description
Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register (SCFSR).
The RDF flag is set to 1 when the quantity of receive
data stored in the receive FIFO register (SCFRDR) is
increased more than the set trigger number shown
below.
•
Note: In clock synchronous mode, to transfer the
Transmit FIFO Data Trigger
Set the quantity of remaining transmit data which sets
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set to 1
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set
trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
Section 15 Serial Communication Interface with FIFO (SCIF)
Asynchronous mode •
00: 1
01: 4
10: 8
11: 14
receive data using DMAC, set the receive trigger
number to 1. If set to other than 1, CPU must
read the receive data left in SCFRDR.
empty bytes in SCFTDR when the TDFE flag is
set to 1.
Rev. 2.00 Dec. 09, 2005 Page 751 of 1152
Clocked synchronous mode
00: 1
01: 2
10: 8
11: 14
REJ09B0191-0200