r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 756

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Dec. 09, 2005 Page 732 of 1152
REJ09B0191-0200
Bit
6
5
Bit Name
RIE
TE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables the receive FIFO data full (RXI)
interrupts requested when the RDF flag or DR flag in
serial status register (SCFSR) is set to1, receive-error
(ERI) interrupts requested when the ER flag in SCFSR
is set to1, and break (BRI) interrupts requested when
the BRK flag in SCFSR or the ORER flag in line status
register (SCLSR) is set to1.
0: Receive FIFO data full interrupt (RXI), receive-error
1: Receive FIFO data full interrupt (RXI), receive-error
Note: * RXI interrupt requests can be cleared by
Transmit Enable
Enables or disables the serial transmitter.
0: Transmitter disabled
1: Transmitter enabled*
Note: * Serial transmission starts after writing of
interrupt (ERI), and break interrupt (BRI) requests
are disabled
interrupt (ERI), and break interrupt (BRI) requests
are enabled*
reading the DR or RDF flag after it has been
set to 1, then clearing the flag to 0, or by
clearing RIE to 0. ERI or BRI interrupt requests
can be cleared by reading the ER, BR or
ORER flag after it has been set to 1, then
clearing the flag to 0, or by clearing RIE and
REIE to 0.
transmit data into SCFTDR. Select the transmit
format in SCSMR and SCFCR and reset the
transmit FIFO before setting TE to 1.