r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 370

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
No. Condition
[5]
[6]
[7]
[8]
Rev. 2.00 Dec. 09, 2005 Page 346 of 1152
REJ09B0191-0200
Read data
transfer cycle
Internal bus
idle cycles, etc.
Write data wait
cycles
Idle cycles
between
different
memory types
Description
One idle cycle is inserted after a
read access is completed. This idle
cycle is not generated for the first or
middle cycles in divided access
cycles. This is neither generated
when the HM[1:0] bits in CSnWCR
are not B'00.
External bus access requests from
the CPU or DMAC and their results
are passed through the internal
bus. The external bus enters idle
state during internal bus idle cycles
or while a bus other than the
external bus is being accessed.
This condition is not effective for
divided access cycles, which are
generated by the BSC when the
access size is larger than the
external data bus width.
During write access, a write cycle is
executed on the external bus only
after the write data becomes ready.
This write data wait period
generates idle cycles before the
write cycle. Note that when the
previous cycle is a write cycle and
the internal bus idle cycles are
shorter than the previous write
cycle, write data can be prepared in
parallel with the previous write cycle
and therefore, no idle cycle is
generated (write buffer effect).
To ensure the minimum pulse width
on the signal-multiplexed pins, idle
cycles may be inserted before
access after memory types are
switched. For some memory types,
idle cycles are inserted even when
memory types are not switched.
Range
0 or 1
0 or
larger
0 or 1
0 to 2.5 The number of idle cycles
Note
One idle cycle is always
generated after a read cycle
with SDRAM or PCMCIA
interface.
The number of internal bus
idle cycles may not become 0
depending on the Iφ:Bφ clock
ratio. Tables 8.19 and 8.20
show the relationship between
the clock ratio and the
minimum number of internal
bus idle cycles.
For write → write or write →
read access cycles,
successive access cycles
without idle cycles are
frequently available due to the
write buffer effect described in
the left column. If successive
access cycles without idle
cycles are not allowed, specify
the minimum number of idle
cycles between access cycles
through CSnBCR.
depends on the target memory
types. See table 8.21.