r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 394

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Direct Memory Access Controller (DMAC)
Rev. 2.00 Dec. 09, 2005 Page 370 of 1152
REJ09B0191-0200
Bit
19
18
Bit Name
HE
HIE
Initial
Value
0
0
R/W
R/(W)* Half-End Flag
R/W
Descriptions
This bit is set to 1 when the transfer count reaches half
of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set
to 1. If DMA transfer ends due to an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR after the HE bit is set to 1, the bit
remains set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.
0: DMATCR > (DMATCR set before transfer starts)/2
[Clearing condition]
•
1: DMATCR ≤ (DMATCR set before transfer starts)/2
Half-End Interrupt Enable
Specifies whether to issue an interrupt request to the
CPU when the transfer count reaches half of the
DMATCR value that was specified before transfer
starts.
When the HIE bit is set to 1, the DMAC requests an
interrupt to the CPU when the HE bit becomes 1.
0: Disables an interrupt to be issued when DMATCR
1: Enables an interrupt to be issued when DMATCR
during DMA transfer or after DMA transfer is
terminated
= (DMATCR set before transfer starts)/2
= (DMATCR set before transfer starts)/2
Writing 0 after reading HE = 1.