r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 533

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Table 10.45 show the TICCR setting and input capture input pins.
Table 10.45 TICCR Setting and Input Capture Input Pins
(1)
Figure 10.20 shows an example of the setting procedure for cascaded operation.
(2)
Figure 10.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Target Input Capture
Input capture from TCNT_1 to
TGRA_1
Input capture from TCNT_1 to
TGRB_1
Input capture from TCNT_2 to
TGRA_2
Input capture from TCNT_2 to
TGRB_2
Example of Cascaded Operation Setting Procedure
Cascaded Operation Example (a)
<Cascaded operation>
Cascaded operation
Set cascading
Start count
Figure 10.20 Cascaded Operation Setting Procedure
TICCR Setting
I2AE bit = 0 (initial value)
I2AE bit = 1
I2BE bit = 0 (initial value)
I2BE bit = 1
I1AE bit = 0 (initial value)
I1AE bit = 1
I1BE bit = 0 (initial value)
I1BE bit = 1
[1]
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
[2] Set the CST bit in TSTR for the upper and
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
lower channel to 1 to start the count
operation.
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Dec. 09, 2005 Page 509 of 1152
Input Capture Input Pins
TIOC1A
TIOC1A, TIOC2A
TIOC1B
TIOC1B, TIOC2B
TIOC2A
TIOC2A, TIOC1A
TIOC2B
TIOC2B, TIOC1B
REJ09B0191-0200

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