r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 828

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
16.4
The I
mode by setting FS in SAR.
16.4.1
Figure 16.3 shows the I
following a start condition always consists of eight bits.
[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
Rev. 2.00 Dec. 09, 2005 Page 804 of 1152
REJ09B0191-0200
SDA
SCL
(a) I
(b) I
S
S
1
1
2
2
2
C bus interface 3 can communicate either in I
C bus format (FS = 0)
C bus format (Start condition retransmission, FS = 0)
S
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
Acknowledge. The receive device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
R/W is 1, or from the master device to the slave device when R/W is 0.
Operation
I
SLA
SLA
2
7
2
C Bus Format
7
C Bus Interface 3 (IIC3)
SLA
1-7
1
1
R/W
R/W
1
1
2
C bus formats. Figure 16.4 shows the I
R/W
8
A
A
1
1
DATA
DATA
A
9
n1
Figure 16.3 I
n
Figure 16.4 I
m1
A
1
A/A
1-7
1
m
DATA
S
1
2
C Bus Formats
2
C Bus Timing
2
C bus mode or clocked synchronous serial
8
SLA
7
A/A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
1
A
9
1
2
R/W
P
C bus timing. The first frame
1
1
A
1
1-7
DATA
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
DATA
n2
m2
8
9
A
A/A
1
P
1
P