r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 195

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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 Whether or not an access issued on the C bus by the CPU is issued on the I bus depends on
 When a break condition is specified for the I bus, only the data access cycle is monitored.
 The DMAC only issues data access cycles for I bus cycles.
 If a break condition is specified for the I bus, even when the condition matches in an I bus
the cache settings. Regarding the I bus operation under cache conditions, see table 7.8 in
section 7, Cache.
The instruction fetch cycle (including the cache renewal cycle) is not monitored.
cycle resulting from an instruction executed by the CPU, at which instruction the user
break interrupt request is to be accepted cannot be clearly defined.
Rev. 2.00 Dec. 09, 2005 Page 171 of 1152
Section 6 User Break Controller (UBC)
REJ09B0191-0200

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