r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 501

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
Table 10.30 Output Level Select Function
Note: The reverse phase waveform initial output value changes to active level after elapse of the
Bit
3
2
1
0
Bit 1
OLSN
0
1
dead time after count start.
2. Clearing the TOCS0 bit to 0 makes this bit setting valid.
Bit Name
TOCL
TOCS
OLSN
OLSP
Initial Output
High level
Low level
control.
Initial
value
0
0
0
0
Active Level
Low level
High level
R/W
R/(W)*
R/W
R/W
R/W
1
Description
TOC Register Write Protection*
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
1: Write access to the TOCS, OLSN, and OLSP bits is
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
Output Level Select N*
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.30.
Output Level Select P*
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.31.
Up Count
High level
Low level
enabled
disabled
Function
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Compare Match Output
Rev. 2.00 Dec. 09, 2005 Page 477 of 1152
3
3
Down Count
Low level
High level
2
REJ09B0191-0200