r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 733

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

14.3.2
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
WTCSR is initialized to H'18 by a power-on reset caused by the RES pin or in software standby
mode. When used to count the clock oscillation settling time for canceling software standby mode,
it retains its value after counter overflow.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
Bit
7
6
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Watchdog Timer Control/Status Register (WTCSR)
Bit Name
IOVF
WT/IT
Initial value:
Initial
Value
0
0
R/W:
Bit:
R/(W) R/W
IOVF
7
0
R/W
R/(W)
R/W
WT/IT
6
0
R/W
TME
Description
Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This flag is not set in watchdog timer mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
•
Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Use as interval timer
1: Use as watchdog timer
Note: When the WTCNT overflows in watchdog timer
5
0
When 0 is written to IOVF after reading IOVF
R
4
1
-
mode, the WDTOVF signal is output externally.
If this bit is modified when the WDT is running,
the up-count may not be performed correctly.
R
3
1
-
Rev. 2.00 Dec. 09, 2005 Page 709 of 1152
R/W
2
0
CKS[2:0]
Section 14 Watchdog Timer (WDT)
R/W
1
0
R/W
0
0
REJ09B0191-0200