r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 403

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

9.3.8
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
DMAOR is initialized to H'00000000 by a power-on reset and retains the value in manual reset,
software standby mode, and module standby mode.
Initial value:
Bit
15, 14
13, 12
11, 10
Note:
R/W:
Bit:
*
DMA Operation Register (DMAOR)
Only 0 can be written to clear the flag after 1 is read.
Bit Name

CMS[1:0]

15
R
0
-
14
R
0
-
R/W
13
0
CMS[1:0]
Initial
Value
All 0
00
All 0
R/W
12
0
11
R
0
-
R/W
R
R/W
R
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
9
0
PR[1:0]
Executes one DMA transfer for every 16 cycles of
Bφ clock.
Executes one DMA transfer for every 64 cycles of
Bφ clock.
R/W
8
0
Section 9 Direct Memory Access Controller (DMAC)
R
7
0
-
Rev. 2.00 Dec. 09, 2005 Page 379 of 1152
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R/(W)* R/(W)* R/W
REJ09B0191-0200
AE
2
0
NMIF
1
0
DME
0
0