r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 575

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

(n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing
occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change
in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval
at the trough as indicated by (10) or (11) in figure 10.56. When synchronous clearing occurs
outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb
interval at the trough, if synchronous clearing occurs in the initial value output period (indicated
by (1) in figure 10.56) immediately after the counters start operation, initial value output is not
suppressed.
This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing
generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM
mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2
can cause counter clearing.
Negative phase
Positive phase
Counter start
TGRA_3
TGRB_3
Mode
H'0000
TCDR
TDDR
Tb interval
(1)
Figure 10.56 Timing for Synchronous Counter Clearing
(2)
(3)
(4)
Tb interval
(5)
(6)
(7)
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(8)
(9)
Rev. 2.00 Dec. 09, 2005 Page 551 of 1152
Tb interval
(10) (11)
Output waveform is active-low
TCNT_3
REJ09B0191-0200
TCNT_4