r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 442

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r5s72060w200fpv

Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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0
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three
(TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted
only when TCNT operation is stopped.
[Legend]
x:
Rev. 2.00 Dec. 09, 2005 Page 418 of 1152
REJ09B0191-0200
Bit
7 to 5
4, 3
2 to 0
Don't care
Bit Name
CCLR[2:0]
CKEG[1:0]
TPSC[2:0]
Timer Control Register (TCR)
Initial value:
Initial
Value
000
00
000
R/W:
Bit:
R/W
7
0
R/W
R/W
R/W
R/W
CCLR[2:0]
R/W
6
0
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 10.4 and 10.5 for details.
Clock Edge 0 and 1
These bits select the input clock edge. When the input
clock is counted using both edges, the input clock
period is halved (e.g. Pφ/4 both edges = Pφ/2 rising
edge). If phase counting mode is used on channels 1
and 2, this setting is ignored and the phase counting
mode setting has priority. Internal clock edge selection
is valid when the input clock is Pφ/4 or slower. When
Pφ/1, or the overflow/underflow of another channel is
selected for the input clock, although values can be
written, counter operation compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
See tables 10.6 to 10.9 for details.
R/W
5
0
R/W
CKEG[1:0]
4
0
R/W
3
0
R/W
2
0
TPSC[2:0]
R/W
1
0
R/W
0
0

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