r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 507

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 10.3 shows an example of the PWM output level setting procedure in buffer operation.
10.3.23 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit
7
6
Bit Name
—
BDC
Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation
Set bit TOCS
Set TOCR2
Set TOLBR
Initial value:
Initial
value
1
0
R/W:
Bit:
[1]
[2]
[3]
R
7
1
-
R/W
R
R/W
BDC
R/W
6
0
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting.
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer
[3] The TOLBR initial setting must be the same value as specified in
Description
Reserved
This bit is always read as 1. The write value should
always be 1.
Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P
to specify the PWM output levels.
bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
R/W
5
N
0
R/W
4
P
0
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
FB
3
0
Rev. 2.00 Dec. 09, 2005 Page 483 of 1152
R/W
WF
2
0
R/W
VF
1
0
R/W
UF
0
0
REJ09B0191-0200