r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1008

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 22 Power-Down Modes
• Canceling with a reset
Rev. 2.00 Dec. 09, 2005 Page 984 of 1152
REJ09B0191-0200
The clock output phase of the CKIO pin may be unstable immediately after detecting an
interrupt and until software standby mode is canceled. When software standby mode is
canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters
software standby mode (when the clock pulse stops) and should be low when the CPU returns
from software standby mode (when the clock is initiated after the oscillation settling). When
software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should be
low when the CPU enters software standby mode (when the clock pulse stops) and should be
high when the CPU returns from software standby mode (when the clock is initiated after the
oscillation settling) (This is the same with the IRQ pin.)
When the RES pin is driven low, software standby mode is released and this LSI enters the
power-on reset state. And if the RES pin is driven high after that, the power-on reset exception
handling starts.
When the MRES pin is driven low followed by being driven high, software standby mode is
released the manual reset exception handling starts on the condition that the frequency ratio of
the internal clock (Iφ) to the peripheral clock (Pφ) is 6:1, 8:1, or 12:1. If the ratio is either 1:1,
2:1, 3:1, or 4:1, the manual reset exception handling is not generated and the instruction next to
the SLEEP instruction is executed. To generate the manual reset exception handling, set the
frequency ratio of (Iφ) to (Pφ) to 6:1, 8:1, or 12:1 before transferring to software standby
mode.
Keep the RES or MRES pin low until the clock oscillation settles.