r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 241

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
20
19, 18
17, 16
15 to 13
12, 11
Bit Name
BAS*

*

SW[1:0]
Initial
Value
0
All 0
All 0
All 0
00
R/W
R/W
R
R/W
R
R/W
Description
Byte Access Selection when SRAM with Byte
Selection is Used
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
1: Asserts the WEn signal during the read/write access
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
Set this bit to 0 when the interface for normal space or
SRAM with byte selection is used.
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CS0 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
cycle and asserts the RD/WR signal at the write
timing.
asserts the RD/WR signal during the write access
cycle.
Rev. 2.00 Dec. 09, 2005 Page 217 of 1152
Section 8 Bus State Controller (BSC)
REJ09B0191-0200