r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 419

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

(1)
(a)
In dual address mode, both the transfer source and destination are accessed (selected) by an
address. The transfer source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
9.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is
written to the other external memory in a data write cycle.
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the
channel control register (CHCR) can specify whether the DACK is output in read cycle or write
cycle.
Figure 9.6 shows an example of DMA transfer timing in dual address mode.
Address Modes
Dual Address Mode
The SAR value is an address, data is read from the transfer source module,
and the data is tempolarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
DMAC
DMAC
Figure 9.5 Data Flow of Dual Address Mode
SAR
DAR
SAR
DAR
Second bus cycle
First bus cycle
Section 9 Direct Memory Access Controller (DMAC)
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
Rev. 2.00 Dec. 09, 2005 Page 395 of 1152
module
module
module
module
REJ09B0191-0200