r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 176

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller (INTC)
5.8.3
If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the
CPU in a state where saving has been performed to all register banks, automatic saving to the
stack is performed instead of register bank saving if the BOVE bit in the bank number register
(IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception
occurs and data is not saved to the stack.
Save and restore operations when using the stack are as follows:
(1)
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt
2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to
3. The register bank overflow bit (BO) in SR is set to 1.
4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
(2)
When the RESBANK (restore from register bank) instruction is executed with the register bank
overflow bit (BO) in SR set to 1, the CPU operates as follows:
1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored
2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
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REJ09B0191-0200
exception handling.
the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14,
R13, …, R1, and R0.
maximum value of 15.
from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14,
PR, GBR, MACH, and MACL.
maximum value of 15.
Saving to Stack
Restoration from Stack
Save and Restore Operations after Saving to All Banks