r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 735

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

14.3.3
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
WRCSR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by
the internal reset signal generated by overflow of the WDT. WRCSR is initialized to H'1F in
software standby mode.
Note: The method for writing to WRCSR differs from that for other registers to prevent
Bit
7
6
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Watchdog Reset Control/Status Register (WRCSR)
Bit Name
WOVF
RSTE
Initial value:
Initial
Value
0
0
R/W:
Bit:
WOVF RSTE
R/(W) R/W
7
0
R/W
R/(W)
R/W
6
0
RSTS
R/W
Description
Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
•
Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
5
0
When 0 is written to WOVF after reading WOVF
R
4
1
-
WTCSR reset within WDT.
R
3
1
-
Rev. 2.00 Dec. 09, 2005 Page 711 of 1152
R
2
1
-
Section 14 Watchdog Timer (WDT)
R
1
1
-
R
0
1
-
REJ09B0191-0200