r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 189

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.5
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupt requests, (2) including or excluding of the data bus value, (3) bus master of the I bus, (4)
C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or write, and (7) operand
size as the break conditions. BBR is initialized to H'0000 by a power-on reset, but retains its
previous value by a manual reset or in software standby mode or sleep mode.
Initial value:
Bit
15, 14
13
12
11, 10
9, 8
R/W:
Bit:
Break Bus Cycle Register (BBR)
Bit Name

UBID
DBE

CP[1:0]
15
R
0
-
14
R
0
-
UBID
R/W
13
0
Initial
Value
All 0
0
0
All 0
00
R/W
DBE
12
0
11
R
0
-
R/W
R
R/W
R/W
R
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
1: Data bus condition is included in break conditions
Reserved
These bits are always read as 0. The write value
should always be 0.
I-Bus Bus Master Select
Select the bus master when the bus cycle of the break
condition is the I bus cycle. However, when the C bus
cycle is selected, this bit is invalidated (only the CPU
cycle).
x1: CPU cycle is included in break conditions
1x: DMAC cycle is included in break conditions
R/W
9
0
CP[1:0]
conditions
R/W
8
0
R/W
7
0
CD[1:0]
Rev. 2.00 Dec. 09, 2005 Page 165 of 1152
R/W
6
0
Section 6 User Break Controller (UBC)
R/W
5
0
ID[1:0]
R/W
4
0
R/W
3
0
RW[1:0]
REJ09B0191-0200
R/W
2
0
R/W
1
0
SZ[1:0]
R/W
0
0