r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 101

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Notes:
Caution: 1. The frequency of the internal clock is the frequency of the signal input to the CKIO
Clock
Operating
Mode
7
FRQCR
Setting
H'1333
H'1335
H'1336
H'1404
H'1406
H'1414
H'1416
H'1424
H'1426
H'1444
H'1446
H'1505
H'1515
H'1535
H'1555
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. In mode 2, the frequency of the clock input from the EXTAL pin or the frequency of
2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO
3. The frequency multiplier of PLL circuit 1 can be selected as ×1, ×2, ×3, ×4, ×6, or ×8.
4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the
the crystal resonator. In mode 7, the frequency of the clock input from the CKIO pin.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Do not set a frequency for the internal clock below the frequency of
the signal on the CKIO pin.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Set the frequency of the peripheral clock to 33.33 MHz or below. In
addition, do not set a higher frequency for the internal clock than the frequency on
the CKIO pin.
The divisor of the divider can be selected as ×1, ×1/2, ×1/3, ×1/4, ×1/6, ×1/8, or
×1/12. The settings are made in the frequency-control register (FRQCR).
frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL
circuit 1 is no more than 200 MHz.
PLL
Circuit 1
ON (×4)
ON (×4)
ON (×4)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×8)
ON (×8)
ON (×8)
ON (×8)
PLL Frequency
Multiplier
PLL
Circuit 2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Ratio of
Internal Clock
Frequencies
(I:B:P)*
1:1:1
1:1:1/2
1:1:1/3
6:1:1
6:1:1/2
3:1:1
3:1:1/2
2:1:1
2:1:1/2
1:1:1
1:1:1/2
8:1:1
4:1:1
2:1:1
1:1:1
1
Input Clock*
20 to 33.33
20 to 50
20 to 50
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 25
20 to 25
20 to 25
20 to 25
2
Output Clock
(CKIO Pin)















Selectable Frequency Range (MHz)
Rev. 2.00 Dec. 09, 2005 Page 77 of 1152
Section 3 Clock Pulse Generator (CPG)
Internal Clock
(Iφ)
20 to 33.33
20 to 50
20 to 50
120 to 200
120 to 200
60 to 100
60 to 100
40 to 66.67
40 to 66.67
20 to 33.33
20 to 33.33
160 to 200
80 to 100
40 to 50
20 to 25
Bus Clock
(Bφ)
20 to 33.33
20 to 50
20 to 50
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 25
20 to 25
20 to 25
20 to 25
REJ09B0191-0200
Peripheral
Clock (Pφ)
20 to 33.33
10 to 25
6.67 to 16.67
20 to 33.33
10 to 16.67
20 to 33.33
10 to 16.67
20 to 33.33
10 to 16.67
20 to 33.33
10 to 16.67
20 to 25
20 to 25
20 to 25
20 to 25