r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 18

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

14.4 WDT Usage ....................................................................................................................... 714
14.5 Usage Notes ....................................................................................................................... 719
Section 15 Serial Communication Interface with FIFO (SCIF)........................ 721
15.1 Features.............................................................................................................................. 721
15.2 Input/Output Pins............................................................................................................... 723
15.3 Register Descriptions......................................................................................................... 724
15.4 Operation ........................................................................................................................... 758
15.5 SCIF Interrupts .................................................................................................................. 780
15.6 Usage Notes ....................................................................................................................... 781
Rev. 2.00 Dec. 09, 2005 Page xviii of xxiv
14.3.3 Watchdog Reset Control/Status Register (WRCSR) ............................................ 711
14.3.4 Notes on Register Access ..................................................................................... 712
14.4.1 Canceling Software Standby Mode ...................................................................... 714
14.4.2 Changing the Frequency ....................................................................................... 715
14.4.3 Using Watchdog Timer Mode .............................................................................. 716
14.4.4 Using Interval Timer Mode .................................................................................. 718
14.5.1 Timer Variation .................................................................................................... 719
14.5.2 Prohibition against Setting H'FF to WTCNT........................................................ 719
14.5.3 System Reset by WDTOVF Signal....................................................................... 719
14.5.4 Manual Reset in Watchdog Timer Mode.............................................................. 720
15.3.1 Receive Shift Register (SCRSR) .......................................................................... 726
15.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 726
15.3.3 Transmit Shift Register (SCTSR) ......................................................................... 727
15.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 727
15.3.5 Serial Mode Register (SCSMR)............................................................................ 728
15.3.6 Serial Control Register (SCSCR).......................................................................... 731
15.3.7 Serial Status Register (SCFSR) ............................................................................ 735
15.3.8 Bit Rate Register (SCBRR) .................................................................................. 743
15.3.9 FIFO Control Register (SCFCR) .......................................................................... 750
15.3.10 FIFO Data Count Set Register (SCFDR).............................................................. 753
15.3.11 Serial Port Register (SCSPTR) ............................................................................. 754
15.3.12 Line Status Register (SCLSR) .............................................................................. 756
15.4.1 Overview .............................................................................................................. 758
15.4.2 Operation in Asynchronous Mode ........................................................................ 760
15.4.3 Operation in Clocked Synchronous Mode ............................................................ 771
15.6.1 SCFTDR Writing and TDFE Flag ........................................................................ 781
15.6.2 SCFRDR Reading and RDF Flag ......................................................................... 781
15.6.3 Restriction on DMAC Usage ................................................................................ 782
15.6.4 Break Detection and Processing ........................................................................... 782
15.6.5 Sending a Break Signal......................................................................................... 782