r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 417

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 9.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is
transfer).
waiting)
channels.
(channel 3 waits for transfer).
channels.
given the lowest priority among the round-robin channels.
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1, 3
3
3
None
(2) Channel 0 transfer start
(4) Channel 0 transfer ends
(5) Channel 1 transfer starts
(6) Channel 1 transfer ends
(7) Channel 3 transfer starts
(8) Channel 3 transfer ends
DMAC operation
Section 9 Direct Memory Access Controller (DMAC)
Priority order
changes
Priority order
changes
Priority order
changes
Rev. 2.00 Dec. 09, 2005 Page 393 of 1152
Channel priority
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7
1 > 2 > 3 > 0 > 4 > 5 > 6 > 7
2 > 3 > 0 > 1 > 4 > 5 > 6 > 7
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7
REJ09B0191-0200