r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 250
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r5s72060w200fpv
Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S72060W200FPV.pdf
(1180 pages)
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Part Number:
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Part Number:
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Manufacturer:
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Section 8 Bus State Controller (BSC)
Rev. 2.00 Dec. 09, 2005 Page 226 of 1152
REJ09B0191-0200
Bit
15 to 13
12, 11
10 to 7
Bit Name
SW[1:0]
WR[3:0]
Initial
Value
All 0
00
1010
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CS4 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS4 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
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