r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 123

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

4.4
4.4.1
(1)
In the state where saving has already been performed to all register bank areas, bank overflow
occurs when acceptance of register bank overflow exception has been set by the interrupt
controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
(2)
Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving
has not been performed to register banks.
4.4.2
When a register bank error occurs, register bank error exception handling starts. The CPU operates
as follows:
1. The exception service routine start address which corresponds to the register bank error that
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the exception service routine start address fetched from the exception
occurred is fetched from the exception handling vector table.
instruction to be executed after the last executed instruction for a bank overflow, and the start
address of the executed RESBANK instruction for a bank underflow.
To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level
that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status
register (SR).
handling vector table, program execution starts. The jump that occurs is not a delayed branch.
Bank Overflow
Bank Underflow
Register Bank Errors
Register Bank Error Sources
Register Bank Error Exception Handling
Rev. 2.00 Dec. 09, 2005 Page 99 of 1152
Section 4 Exception Handling
REJ09B0191-0200