r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 855

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

17.3.1
The sixteen A/D data registers, ADDRA_0 to ADDRH_0 (A/D0) and ADDRA_1 to ADDRH_1
(A/D1), are 16-bit read-only registers that store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the ADDR
corresponding to the selected channel. The 10 bits of the result are stored in the upper bits (bits 15
to 6) of ADDR. Bits 5 to 0 of ADDR are reserved bits that are always read as 0.
Access to ADDR in 8-bit units is prohibited. ADDR must always be accessed in 16-bit units.
ADDR is initialized to H'0000 by a power-on reset or in software standby mode or module
standby mode.
Table 17.3 indicates the pairings of analog input channels and ADDR.
Initial value:
Bit
15 to 6
5 to 0
R/W:
Bit:
A/D Data Registers A to H (ADDRA to ADDRH)
Bit Name

15
R
0
14
R
0
13
R
0
Initial
Value
All 0
All 0
12
R
0
11
R
0
R/W
R
R
10
R
0
Description
Bit data (10 bits)
Reserved
These bits are always read as 0. The write value
should always be 0.
R
9
0
R
8
0
R
7
0
Rev. 2.00 Dec. 09, 2005 Page 831 of 1152
R
6
0
Section 17 A/D Converter (ADC)
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0191-0200
R
2
0
-
R
1
0
-
R
0
0
-