r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 483

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

10.3.8
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit
7 to 4
3
2
1
Bit Name
—
I2BE
I2AE
I1BE
Timer Input Capture Control Register (TICCR)
Initial value:
Initial
Value
All 0
0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Input Capture Enable
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
1: Includes the TIOC2B pin in the TGRB_1 input
Input Capture Enable
Specifies whether to include the TIOC2A pin in the
TGRA_1 input capture conditions.
0: Does not include the TIOC2A pin in the TGRA_1
1: Includes the TIOC2A pin in the TGRA_1 input
Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
1: Includes the TIOC1B pin in the TGRB_2 input
R
5
0
-
capture conditions
capture conditions
capture conditions
input capture conditions
input capture conditions
input capture conditions
R
4
0
-
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
I2BE
3
0
Rev. 2.00 Dec. 09, 2005 Page 459 of 1152
R/W
I2AE
2
0
R/W
I1BE
1
0
R/W
I1AE
0
0
REJ09B0191-0200