r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 720

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 Compare Match Timer (CMT)
13.2.2
CMCSR is a 16-bit register that indicates compare match generation, enables or disables
interrupts, and selects the counter input clock.
CMCSR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Initial value:
Rev. 2.00 Dec. 09, 2005 Page 696 of 1152
REJ09B0191-0200
Bit
15 to 8
7
6
5 to 2
Note:
R/W:
Bit:
*
Compare Match Timer Control/Status Register (CMCSR)
Only 0 can be written to clear the flag after 1 is read.
Bit Name

CMF
CMIE

15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
0
All 0
12
R
0
-
R/W
R
R/(W)* Compare Match Flag
R/W
R
11
R
0
-
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Indicates whether or not the values of CMCNT and
CMCOR match.
0: CMCNT and CMCOR values do not match
[Clearing condition]
•
1: CMCNT and CMCOR values match
Compare Match Interrupt Enable
Enables or disables compare match interrupt (CMI)
generation when CMCNT and CMCOR values match
(CMF = 1).
0: Compare match interrupt (CMI) disabled
1: Compare match interrupt (CMI) enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
When 0 is written to CMF after reading CMF = 1
R
9
0
-
R
8
0
-
R/(W)* R/W
CMF
7
0
CMIE
6
0
R
5
0
-
R
4
0
-
R
3
0
-
R
2
0
-
R/W
1
0
CKS[1:0]
R/W
0
0