r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 203

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

7.1
• Capacity
• Structure: Instructions/data separated, 4-way set associative
• Cache lock function (only for operand cache): Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 128 entries/way
• Write system: Write-back/write-through selectable
• Replacement method: Least-recently-used (LRU) algorithm
7.1.1
The cache separates data and instructions and uses a 4-way set associative system. It is composed
of four ways (banks), each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 128 entries. The data section of the entry is
called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2 Kbytes
(16 bytes × 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure 7.1
shows the operand cache structure. The instruction cache structure is the same as the operand
cache structure except for not having the U bit.
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
Features
Cache Structure
Section 7 Cache
Rev. 2.00 Dec. 09, 2005 Page 179 of 1152
REJ09B0191-0200
Section 7 Cache