r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 12

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

5.10 Usage Note......................................................................................................................... 156
Section 6 User Break Controller (UBC)............................................................ 157
6.1
6.2
6.3
6.4
6.5
Section 7 Cache ................................................................................................. 179
7.1
7.2
7.3
7.4
Rev. 2.00 Dec. 09, 2005 Page xii of xxiv
5.9.1
5.9.2
5.10.1 Timing to Clear an Interrupt Source ..................................................................... 156
Features.............................................................................................................................. 157
Input/Output Pin ................................................................................................................ 159
Register Descriptions......................................................................................................... 160
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Operation ........................................................................................................................... 170
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Usage Notes ....................................................................................................................... 178
Features.............................................................................................................................. 179
7.1.1
Register Descriptions......................................................................................................... 182
7.2.1
7.2.2
Operation ........................................................................................................................... 188
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
Memory-Mapped Cache .................................................................................................... 194
7.4.1
Handling Interrupt Request Signals as Sources for CPU Interrupt but Not
DMAC Activating ................................................................................................ 155
Handling Interrupt Request Signals as Sources for Activating DMAC but Not
CPU Interrupt........................................................................................................ 155
Break Address Register (BAR)............................................................................. 161
Break Address Mask Register (BAMR) ............................................................... 162
Break Data Register (BDR) .................................................................................. 163
Break Data Mask Register (BDMR)..................................................................... 164
Break Bus Cycle Register (BBR) ......................................................................... 165
Break Control Register (BRCR) ........................................................................... 167
Flow of the User Break Operation ........................................................................ 170
Break on Instruction Fetch Cycle ......................................................................... 172
Break on Data Access Cycle................................................................................. 173
Value of Saved Program Counter ......................................................................... 174
Usage Examples.................................................................................................... 175
Cache Structure..................................................................................................... 179
Cache Control Register 1 (CCR1) ........................................................................ 182
Cache Control Register 2 (CCR2) ........................................................................ 184
Searching Cache ................................................................................................... 188
Read Access.......................................................................................................... 190
Prefetch Operation (Only for Operand Cache) ..................................................... 190
Write Operation (Only for Operand Cache) ......................................................... 191
Write-Back Buffer (Only for Operand Cache) ..................................................... 191
Coherency of Cache and External Memory.......................................................... 193
Address Array....................................................................................................... 194