r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 168

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Interrupt Controller (INTC)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
Rev. 2.00 Dec. 09, 2005 Page 144 of 1152
REJ09B0191-0200
Item
Interrupt
response time
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (Iφ, Bφ, Pφ) = (200 MHz, 66 MHz, 33 MHz).
No register
banking
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
stack.
Min.
Max.
Min.
Max.
Min.
Max.
NMI
5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
2 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3




User Break
6 Icyc +
m1 + m2
7 Icyc +
2(m1 + m2) +
m3




Number of States
H-UDI
5 Icyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Pcyc +
2(m1 + m2) +
m3
5 Icyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc + m1 +
m2 + 19(m4)
IRQ, PINT
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
3 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc + m1 +
m2 + 19(m4)
Peripheral
Module
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc + m1 +
m2 + 19(m4)
Remarks
200-MHz operation*
0.040 to 0.110 µs
200-MHz operation*
0.060 to 0.130 µs
200-MHz operation*
0.040 to 0.110 µs
200-MHz operation*
0.085 to 0.155 µs
200-MHz operation*
0.040 to 0.110 µs
200-MHz operation*
0.135 to 0.205 µs
1
1
1
1
1
1
*
*
*
*
*
*
2
2
2
2
2
2
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