r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1171

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Global base register (GBR) ...................... 31
H
High-performance user debugging
interface (H-UDI) ................................... 989
H-UDI commands................................... 992
H-UDI interrupt .............................. 127, 995
H-UDI related pin timing...................... 1116
H-UDI reset ............................................ 995
I
I/O port timing ...................................... 1115
I/O ports.................................................. 937
I
I
IIC3 module timing .............................. 1113
Immediate data ......................................... 38
Immediate data accessing ......................... 38
Immediate data format.............................. 35
Initial values of control registers .............. 33
Initial values of general registers .............. 33
Initial values of system registers............... 33
Instruction features ................................... 36
Instruction format ..................................... 45
Instruction set ........................................... 49
Integer division instructions ................... 105
Interrupt controller (INTC)..................... 111
Interrupt exception handling................... 102
Interrupt exception handling vectors
and priorities ........................................... 131
Interrupt priority level............................. 101
Interrupt response time ........................... 143
IRQ interrupts ......................................... 128
J
Jump table base register (TBR) ................ 31
2
2
C bus format......................................... 804
C bus interface 3 (IIC3) ....................... 785
L
Load-store architecture ............................. 36
Logic operation instructions...................... 61
Low-frequency mode .............................. 316
Low-power SDRAM............................... 321
LRU ........................................................ 181
M
Manual reset.............................................. 96
Master receive operation......................... 807
Master transmit operation ....................... 805
Memory-mapped cache........................... 194
Module standby function ........................ 986
MPX-I/O interface .................................. 276
MTU2 functions...................................... 408
MTU2 interrupts ..................................... 589
MTU2 output pin initialization ............... 621
MTU2, MTU2S module timing ............ 1110
MTU2–MTU2S synchronous
operation ................................................. 577
MTU2S functions.................................... 654
Multi mode.............................................. 840
Multi-function timer pulse unit 2
(MTU2)................................................... 407
Multi-function timer pulse unit 2S
(MTU2S)................................................. 653
Multiplexed pins (port A) ....................... 863
Multiplexed pins (port B)........................ 864
Multiplexed pins (port C)........................ 864
Multiplexed pins (port D) ....................... 865
Multiplexed pins (port E)........................ 866
Multiplexed pins (port F) ........................ 867
Multiply and accumulate register high
(MACH).................................................... 32
Multiply and accumulate register low
(MACL) .................................................... 32
Multiply/Multiply-and-accumulate
operations.................................................. 37
Rev. 2.00 Dec. 09, 2005 Page 1147 of 1152
REJ09B0191-0200