r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 478
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r5s72060w200fpv
Manufacturer Part Number
r5s72060w200fpv
Description
32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S72060W200FPV.pdf
(1180 pages)
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Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR2_0
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 2.00 Dec. 09, 2005 Page 454 of 1152
REJ09B0191-0200
Bit
7, 6
5 to 2
1
0
2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after
Bit Name
—
—
TGFF
TGFE
reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is
held.
Note:
1.
Initial value:
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Value
All 1
All 0
0
0
R/W:
Bit:
R
7
1
-
R/W
R
R
R/(W)*
R/(W)*
R
6
1
-
1
1
R
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Compare Match Flag F
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRF_0.
[Clearing condition]
•
[Setting condition]
•
Compare Match Flag E
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRE_0.
[Clearing condition]
•
[Setting condition]
•
5
0
-
When 0 is written to TGFF after reading
TGFF = 1*
When TCNT_0 = TGRF_0 and TGRF_0 is
functioning as compare register
When 0 is written to TGFE after reading
TGFE = 1*
When TCNT_0 = TGRE_0 and TGRE_0 is
functioning as compare register
R
4
0
-
R
3
0
-
2
2
R
2
0
-
R/(W)*
TGFF
1
0
1
R/(W)*
TGFE
0
0
1
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