r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 427

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

9.4.5
(1)
When the DMAC is the bus master, the number of bus cycles is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 8,
Bus State Controller (BSC).
(2)
Figures 9.13 to 9.16 show the DREQ input sampling timings in each bus mode.
Figure 9.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
Figure 9.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Number of Bus Cycles
DREQ Pin Sampling Timing
Number of Bus Cycles and DREQ Pin Sampling Timing
CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
(Rising)
(Active-high)
CKIO
Bus cycle
DREQ
DACK
1st acceptance
1st acceptance
1st acceptance
Non sensitive period
CPU
CPU
CPU
Non sensitive period
Non sensitive period
CPU
CPU
CPU
Section 9 Direct Memory Access Controller (DMAC)
2nd acceptance
Rev. 2.00 Dec. 09, 2005 Page 403 of 1152
DMAC
DMAC
Acceptance
start
DMAC
Acceptance start
2nd acceptance
2nd acceptance
Acceptance
start
CPU
CPU
CPU
REJ09B0191-0200