r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 792

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Dec. 09, 2005 Page 768 of 1152
REJ09B0191-0200
Figure 15.8 Sample Flowchart for Receiving Serial Data (cont)
Read receive data in SCFRDR
and ORER flag in SCLSR to 0
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
in SCFSR,
BRK = 1?
ER = 1?
DR = 1?
End
Yes
Yes
Yes
Yes
No
No
No
No
• Whether a framing error or parity error
• When a break signal is received,
has occurred in the receive data that
is to be read from the receive FIFO
data register (SCFRDR) can be
ascertained from the FER and PER
bits in the serial status register
(SCFSR).
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.