r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 329

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only access cycles to the respective banks in the area 3 space are
considered, as long as access cycles to the same row address continue, the operation starts with the
cycle in figure 8.23 or 8.26, followed by repetition of the cycle in figure 8.24 or 8.27. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 8.24 or 8.27 is executed instead of
that in figure 8.25 or 8.28. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
Figure 8.23 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
RASL, RASU
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
2. The waveform for DACKn is when active low is specified.
CS3
BS
1
2
Tr
Tc1
Td1
Tc2
Td2
Tc3
Rev. 2.00 Dec. 09, 2005 Page 305 of 1152
Td3
Tc4
Section 8 Bus State Controller (BSC)
Td4
Tde
REJ09B0191-0200