r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1170

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Clock operating modes ............................. 74
Clock pulse generator (CPG).................... 69
Clock timing ......................................... 1067
Clocked synchronous serial format ........ 814
CMCNT count timing............................. 699
Coherency of cache and external
memory................................................... 193
Compare match timer (CMT) ................. 693
Complementary PWM mode .................. 528
Conditions for determining number of
idle cycles ............................................... 345
Conflict between byte-write and
count-up processes of CMCNT .............. 704
Conflict between word-write and
count-up processes of CMCNT .............. 703
Conflict between write and
compare-match processes of CMCNT.... 702
Control signal timing ............................ 1070
CPU .......................................................... 29
Crystal oscillator....................................... 71
CSn assert period expansion................... 275
Cycle steal mode..................................... 398
D
D/A converter (DAC) ............................. 855
D/A converter characteristics ............... 1120
D/A output hold function in software
standby mode.......................................... 861
Data array ....................................... 180, 195
Data array read ....................................... 195
Data array write ...................................... 195
Data format in registers ............................ 34
Data formats in memory ........................... 34
Data transfer instructions.......................... 54
Data transfer with interrupt request
signals..................................................... 154
DC characteristics................................. 1061
Dead time compensation ........................ 584
Deep power-down mode......................... 323
Rev. 2.00 Dec. 09, 2005 Page 1146 of 1152
REJ09B0191-0200
Definitions of A/D conversion
accuracy .................................................. 849
Delayed branch instructions...................... 37
Direct memory access controller
(DMAC).................................................. 357
Displacement accessing ............................ 39
Divider 1 ................................................... 71
Divider 2 ................................................... 71
DMA transfer flowchart.......................... 386
DMAC activation.................................... 590
DMAC module timing .......................... 1108
DREQ pin sampling timing .................... 403
Dual address mode.................................. 395
E
Effective address calculation .................... 40
Electrical characteristics ....................... 1059
Endian ..................................................... 265
Equation for getting SCBRR value......... 743
Exception handling ................................... 87
Exception handling state ........................... 68
Exception handling vector table................ 91
Exception source generation
immediately after delayed branch
instruction ............................................... 106
Exceptions triggered by instructions....... 103
External pulse width measurement ......... 583
External request mode............................. 387
External trigger input timing................... 847
F
Fixed mode ............................................. 391
Full-scale error........................................ 849
G
General illegal instructions ..................... 104
General registers ....................................... 29