r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 17

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

12.4 Operation ........................................................................................................................... 687
12.5 Interrupts............................................................................................................................ 691
Section 13 Compare Match Timer (CMT) ........................................................693
13.1 Features.............................................................................................................................. 693
13.2 Register Descriptions ......................................................................................................... 694
13.3 Operation ........................................................................................................................... 699
13.4 Interrupts............................................................................................................................ 700
13.5 Usage Notes ....................................................................................................................... 702
Section 14 Watchdog Timer (WDT)..................................................................705
14.1 Features.............................................................................................................................. 705
14.2 Input/Output Pin................................................................................................................. 707
14.3 Register Descriptions ......................................................................................................... 708
12.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 667
12.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 671
12.3.3 Input Level Control/Status Register 2 (ICSR2) .................................................... 672
12.3.4 Output Level Control/Status Register 2 (OCSR2) ................................................ 676
12.3.5 Input Level Control/Status Register 3 (ICSR3) .................................................... 677
12.3.6 Software Port Output Enable Register (SPOER) .................................................. 679
12.3.7 Port Output Enable Control Register 1 (POECR1)............................................... 681
12.3.8 Port Output Enable Control Register 2 (POECR2)............................................... 682
12.4.1 Input Level Detection Operation........................................................................... 688
12.4.2 Output-Level Compare Operation ........................................................................ 689
12.4.3 Release from High-Impedance State..................................................................... 690
13.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 695
13.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 696
13.2.3 Compare Match Counter (CMCNT) ..................................................................... 698
13.2.4 Compare Match Constant Register (CMCOR) ..................................................... 698
13.3.1 Interval Count Operation ...................................................................................... 699
13.3.2 CMCNT Count Timing......................................................................................... 699
13.4.1 Interrupt Sources and DMA Transfer Requests .................................................... 700
13.4.2 Timing of Compare Match Flag Setting ............................................................... 700
13.4.3 Timing of Compare Match Flag Clearing............................................................. 701
13.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 702
13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 703
13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 704
13.5.4 Compare Match Between CMCNT and CMCOR ................................................ 704
14.3.1 Watchdog Timer Counter (WTCNT).................................................................... 708
14.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 709
Rev. 2.00 Dec. 09, 2005 Page xvii of xxiv