r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 254

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 Bus State Controller (BSC)
Rev. 2.00 Dec. 09, 2005 Page 230 of 1152
REJ09B0191-0200
Bit
12, 11
10 to 7
6
5 to 2
Bit Name
SW[1:0]
WR[3:0]
WM

Initial
Value
00
1010
0
All 0
R/W
R/W
R/W
R/W
R
Description
Number of Delay Cycles from Address, CS5 Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CS5 assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
Reserved
These bits are always read as 0. The write value
should always be 0.