r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 776

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Dec. 09, 2005 Page 752 of 1152
REJ09B0191-0200
Bit
3
2
1
0
Bit Name
MCE
TFRST
RFRST
LOOP
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Transmit FIFO Data Register Reset
Receive FIFO Data Register Reset
Loop-Back Test
Description
Modem Control Enable
Enables modem control signals CTS and RTS.
For channels 0 to 2 in clocked synchronous mode, MCE
bit should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
Internally connects the transmit output pin (TxD) and
receive input pin (RxD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
value, and RTS is also fixed at 0.
reset.
reset.