r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 791

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

• Receiving Serial Data (Asynchronous Mode)
Figures 15.7 and 15.8 show sample flowcharts for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
No
No
Figure 15.7 Sample Flowchart for Receiving Serial Data
ER, DR, BRK or ORER = 1?
Read ER, DR, BRK flags in
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
SCFSR and ORER
flag in SCFSR to 0
All data received?
Start of reception
End of reception
flag in SCLSR
RDF = 1?
No
Yes
Yes
Section 15 Serial Communication Interface with FIFO (SCIF)
Error handling
[1]
[2]
[3]
Yes
[1] Receive error handling and
[2] SCIF status check and receive
[3] Serial reception continuation
Rev. 2.00 Dec. 09, 2005 Page 767 of 1152
break detection:
flags in SCFSR, and the
ORER flag in SCLSR, to
identify any error, perform the
appropriate error handling,
then clear the DR, ER, BRK,
and ORER flags to 0. In the
case of a framing error, a
break can also be detected by
reading the value of the RxD
pin.
data read:
RDF flag = 1, then read the
receive data in SCFRDR, read
1 from the RDF flag, and then
clear the RDF flag to 0. The
transition of the RDF flag from
0 to 1 can also be identified by
a receive FIFO data full
interrupt (RXI).
procedure:
read at least the receive
trigger set number of receive
data bytes from SCFRDR,
read 1 from the RDF flag, then
clear the RDF flag to 0. The
number of receive data bytes
in SCFRDR can be
ascertained by reading from
SCRFDR.
Read the DR, ER, and BRK
Read SCFSR and check that
To continue serial reception,
REJ09B0191-0200