PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 100

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
6.2.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID and Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. The table operations on the TBLPTR only
affect the low-order 21 bits.
TABLE 6-1:
FIGURE 6-3:
DS39762B-page 98
TBLRD*
TBLWT*
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
21
TABLE LATCH REGISTER (TABLAT)
TABLE POINTER REGISTER
(TBLPTR)
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTRU
TABLE POINTER BOUNDARIES BASED ON OPERATION
16
15
TBLPTR<20:10>
TBLPTR<20:6>
Table Erase
Table Write
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
Table Read – TBLPTR<21:0>
TBLPTR is incremented after the read/write
TBLPTRH
Preliminary
Operation on Table Pointer
TBLPTR is not modified
6.2.4
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of the
64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 15 MSbs of the TBLPTR
(TBLPTR<20:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
11 MSbs
(TBLPTR<20:10>) point to the 1024-byte block that will
be erased. The Least Significant bits (TBLPTR<9:0>)
are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
8
7
TABLE POINTER BOUNDARIES
of
the
© 2006 Microchip Technology Inc.
TBLPTRL
Table
Pointer
0
register