PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 314

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
20.2.2
The receiver block diagram is shown in Figure 20-6.
The data is received on the RXx pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
The RXDTP bit (BAUDCON<5>) allows the RXx signal
to be inverted (polarity reversed). Devices that buffer
signals from RS-232 to TTL levels also perform an inver-
sion of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RXx pin data by setting the
RXDTP bit allows for the use of circuits that provide
buffering without inverting the signal.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
DS39762B-page 312
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting bit, SPEN.
If the signal at the RXx pin is to be inverted, set
the RXDTP bit.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
Enable the reception by setting bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
enable bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
EUSARTx ASYNCHRONOUS
RECEIVER
OSC
. This mode would typically be used
Preliminary
20.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read RCREGx to determine if the device is
11. If any error occurred, clear the CREN bit.
12. If the device has been addressed, clear the
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If the signal at the RXx pin is to be inverted, set
the RXDTP bit. If the signal from the TXx pin is
to be inverted, set the TXCKP bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCxIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
being addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
© 2006 Microchip Technology Inc.