PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 235

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5.1.2
The destination address field is a 6-byte field filled with
the MAC address of the device that the packet is
directed to. If the Least Significant bit in the first byte of
the MAC address is set, the address is a Multicast
destination. For example, 01-00-00-00-F0-00 and
33-45-67-89-AB-CD are Multicast addresses, while
00-00-00-00-F0-00 and 32-45-67-89-AB-CD are not.
Packets with Multicast destination addresses are
designed to arrive and be important to a selected group
of Ethernet nodes. If the destination address field is the
reserved Multicast address, FF-FF-FF-FF-FF-FF, the
packet is a Broadcast packet and it will be directed to
everyone sharing the network. If the Least Significant
bit in the first byte of the MAC address is clear, the
address is a Unicast address and will be designed for
usage by only the addressed node.
The Ethernet module incorporates receive filters which
can be used to discard or accept packets with
Multicast,
addresses. When transmitting packets, the application
is responsible for writing the desired destination
address into the transmit buffer.
18.5.1.3
The source address field is a 6-byte field filled with the
MAC address of the node which created the Ethernet
packet. Users of the Ethernet module must generate a
unique
microcontroller used.
MAC addresses consist of two portions. The first three
bytes are known as the Organizationally Unique Identi-
fier (OUI). OUIs are distributed by the IEEE. The last
three bytes are address bytes at the discretion of the
company that purchased the OUI.
When transmitting packets, the assigned source MAC
address must be written into the transmit buffer by the
application. The module will not automatically transmit
the contents of the MAADR registers which are used
for the Unicast receive filter.
18.5.1.4
The type/length field is a 2-byte field which defines
which protocol the following packet data belongs to.
Alternately, if the field is filled with the contents of
05DCh (1500) or any smaller number, the field is
considered a length field, and it specifies the amount of
non-padding data which follows in the data field. Users
implementing proprietary networks may choose to treat
this field as a length field, while applications
implementing protocols such as the Internet Protocol
(IP), or Address Resolution Protocol (ARP), should
program this field with the appropriate type defined by
the protocol’s specification when transmitting packets.
© 2006 Microchip Technology Inc.
MAC
Broadcast
Destination Address
Source Address
Type/Length
address
and/or
for
Unicast
each
and
destination
every
Preliminary
PIC18F97J60 FAMILY
18.5.1.5
The data field is a variable length field anywhere from 0
to 1500 bytes. Larger data packets will violate Ethernet
standards and will be dropped by most Ethernet nodes.
The Ethernet module, however, is capable of transmit-
ting and receiving larger packets when the Huge Frame
Enable bit, HFRMEN, is set (MACON3<2> = 1).
18.5.1.6
The padding field is a variable length field added to
meet IEEE 802.3 specification requirements when
small data payloads are used. The destination, source,
type, data and padding of an Ethernet packet must be
no smaller than 60 bytes. Adding the required 4-byte
CRC field, packets must be no smaller than 64 bytes. If
the data field is less than 46 bytes long, a padding field
is required.
When transmitting packets, the Ethernet module
automatically
PADCFG2:PADCFG0 bits (MACON3<7:5>) are config-
ured for this. Otherwise, the user application will need to
add any padding to the packet before transmitting it. The
module will not prevent the transmission of undersized
packets should the application command such an action.
When receiving packets, the module automatically
rejects packets which are less than 18 bytes. All pack-
ets, 18 bytes and larger, will be subject to the standard
receive filtering criteria and may be accepted as normal
traffic. Since the module only rejects packets smaller
than 18 bytes, it is important that the firmware check
the length of every received packet and reject packets
which are smaller than 64 bytes to meet IEEE 802.3
specification requirements.
18.5.1.7
The CRC field is a 4-byte field which contains an industry
standard, 32-bit CRC, calculated with the data from the
destination, source, type, data and padding fields. It pro-
vides a way of detecting corrupted Ethernet frames, as
well as junk data fragments resulting from packet
collisions or another host’s aborted transmissions.
When receiving packets, the Ethernet module will check
the CRC of each incoming packet. If the CRCEN bit is
set, packets with invalid CRCs will automatically be dis-
carded. If CRCEN is clear and the packet meets all other
receive filtering criteria, the packet will be written into the
receive buffer and the application will be able to deter-
mine if the CRC was valid by reading the receive status
vector (see Section 18.5.3 “Receiving Packets”).
When transmitting packets, the module automatically
generates a valid CRC and transmits it if the
PADCFG2:PADCFG0 bits are configured for this. Other-
wise, the user application must generate the CRC and
place it in the transmit buffer. Given the complexity of
calculating a CRC, it is highly recommended to allow the
module to automatically calculate and include the CRC.
Data
Padding
CRC
generates
zero-padding
DS39762B-page 233
if
the